What is RISC-V and how will it redefine your next-gen wearable tech?

When discussing computer hardware, x86, and ARM are household names when discussing microprocessor architecture. They’ve been around for decades and are still going strong, powering the newest and most powerful CPUs from AMD, Apple, and Intel.

Lately, however, a new challenger is rising. RISC-V seems to be on the rise, and in a few years, it might be running on as many processor cores as ARM or x86. Here’s everything you need to know about the new microprocessor architecture and why it’s getting so popular – it might even soon make its way to the best smartwatches.

What is RISC-V?

For CPUs, especially since Apple transitioned to its own silicon, a lot has been said about x86 and ARM. These two are types of microprocessor architecture, or ISA (Instruction Set Architecture). ISA is a starting point of any CPU design and, in simplest terms, determines what kinds of instructions can be added to the processor and what software can run on it.

RISC-V (pronounced risk five) is another kind of ISA, different from the two dominating ones. The main thing that it brings to the table is its open-source nature. It means that, contrary to proprietary ARM and x86 instructions, the fundamental design of RISC-V is free to use and adapt for anyone interested.

What’s more, RISC-V is a RISC architecture, which stands for Reduced Instruction Set Computer Architecture. Essentially, it means that in its basic form, RISC-V comes with very few instructions. This fact, combined with it being an open standard, means that any company can freely use the stock RISC-V instruction set and modify it easily and efficiently to use it in its custom microprocessor designs.

This model ensures that the foundations of RICS-V are always available for free, but the products that are based on it can still be licensed and sold as ready-made cores.

Brief history of RISC-V

You might think that RISC-V is simply the fifth RISC ISA. It’s unfortunately not that simple, as there have been many more RISC ISAs (for example, ARM is also a RISC architecture). Therefore, RISC-V is quite an arbitrary name that is a throwback to some rather obscure ISA from the 1980s.

Relative to other ISAs, RISC-V is extremely young. It started in Berkeley’s Parallel Computing Lab in 2010. It was presented as a completed ISA in 2014, together with a paper arguing that open-source hardware was the way of the future. A year later, the RISC-V Foundation was created.

Right now, RISC-V is being backed by various tech giants, even those with their own ISAs, such as IBM (who owns PowerPC ISA), Intel (who developed x86 ISA), and Qualcomm (a leading ARM chip designer).

What are the benefits of RISC-V?

So, if even the biggest players in the game are turning their heads towards RISC-V, it must have some undoubtable benefits. Even though x86 architecture in PCs and ARM in mobile devices are the most popular, it doesn’t mean there is no improvement to be made in these spaces. Here are the main benefits of RISC-V and what their impact might be.

• Open-standard nature – RISC-V is an open standard, so companies do not have to pay licensing fees in order to use the basic architecture. This means even smaller companies can develop their cores based on the architecture, and even the biggest players can do it faster, as there is much less red tape involved.
• Ease of modification – RISC-V, as the name suggests, is a RISC (reduced instruction set) architecture. This means it’s much easier to modify and specialize in certain tasks. By making it easier, it also makes creating custom cores faster and cheaper, which can greatly impact the cost of consumer technology.
• Availability of smaller options, focusing on modularity and energy efficiency – Because RISC-V cores are so easy to modify and operate on a RISC (reduced instruction set) architecture, they are easy to scale down and specialize. This means they can do the same task as a general-purpose processor with a fraction of the power needed because they are tailor-made for that task. It makes processors much smaller if they only need to do a certain task.
• Open-source security – being an open-source standard, RISC-V benefits from public scrutiny. As the standard is available in the public domain, it can be scrutinized closely, and all the back doors and hidden channels can be discovered easily.
• Common ISA – RISC-V is a common ISA, meaning that the same basic architecture can be used by different designers to create different cores and processors, from small embedded solutions to big supercomputers. Thanks to that, software development will be much easier, as without architectural differences, all the software could run natively on various different kinds of devices and processors.

How will RISC-V change the next-gen wearables?

As you can see, RISC-V architecture can bring about quite a significant change in the microprocessor space, provided, of course, that all these predictions come true. If they do, RISC-V-based SoCs can be extremely significant, especially for smaller tech devices, such as wearables.

In the case of wearables, the biggest problem that the industry is facing is exactly their size. Because they are so small – they have to fit on your wrist in the form of a watch or get even smaller and fit into a smart ring. That means the batteries are small, and their SoCs are limited in size and power.

That’s where RISC-V architecture comes in. Cores with ROSC-V architecture can be built from the ground up with wearables in mind. Therefore, they can be much more specialized to exactly the use cases needed. It could mean much better energy efficiency for starters, but not only. Suppose a microprocessor is specialized in a particular set of tasks. In that case, it can be much better (faster and more power efficient) even if it’s less powerful than a general-purpose microprocessor. Therefore, creating a specialized set of RISC-V-based microprocessors to handle specialized tasks expected of wearables can make them much faster and substantially more accurate in tracking and extend their battery life.

Therefore, RISC-V architecture is, hopefully, a way of creating better wearables. Their sensors could be read more accurately and efficiently, their batteries could last much longer, and their interfaces could get much smoother. RISC-V seems to be the way to go, provided it delivers on its promises.